1. Thorough understanding of all commonly used Verilog/SystemVerilog constructs, fortified through detailed analysis of simulations using specially designed reference code. 

2. Robust design techniques towards enhancing the reliability, performance, power, area and configurability that are key towards building a successful career in the VLSI design field. 

3. Labs/mini-projects tailored towards developing a systematic design approach, guided by clear instructions combining screen-shots and expert tips. 

4. Progressive design implementation exercises from simple examples to relatively more complex ones, each one coupled with simple SystemVerilog test-bench creation for design sanity checking. 

5. Basic synthesis and gate-netlist schematic analysis exercises that help in building a hardware implementation perspective on top of the HDL coding skills

6. A design-automation example using Perl and exercises that provide a jump-start with Perl programming.

Upon successful completion of the course, the student will:

(1) Have in-depth knowledge and reference examples on SystemVerilog coding constructs. 

(2) Achieve deeper understanding of key aspects related to: 

    →  RTL coding considerations, 

    → Clock requirements

    → Clock-gating

    → Timing analysis

    → Reset

    → Synchronization

    → Finite State Machines

    → Power management

(3) Build sound awareness on the fundamentals of:

    → Design for Test and Manufacturing (DFTM)

    → Power-Performance-Area (PPA) trade-offs

    → Bus Protocols and typical side-band signals

  → Industry standard IP MMR interfaces based on AMBA APB and AXI4-Lite protocols.

(4) Obtain an overview of key aspects related to:

    → Industry Standard IP and SOC design cycles

    → Gate Netlist generation flows

    → Physical design flows

(5) Understand how to systematically plan, partition, implement the RTL and create simple testbenches for simulating/debugging small-medium size IP designs.

(6) Gain confidence with basic IP design through implementation and touch-testing of a hierarchical IP with AMBA APB MMR programming interface and asynchronous clock domains.

(7) Gain sound familiarity with operating in a professional VLSI development environment that includes LINUX OS,usage of Perl programming for automation and ModelSim for simulations.

(8) Take away all the environment needed to conduct trial RTL implementation,  simulations, synthesis and schematic analysis on his/her personal machine using the lab reference material and free EDA tool** installs.

Electronics Engineering graduate students with basic knowledge of digital design and some familiarity with Verilog coding, who want to explore the VLSI engineering field in detail, beyond the scope of their curriculum. 

VLSI Masters students and Professionals entering the VLSI design and verification field, who want to build their career based up on a solid foundation of must-know concepts and good practices adopted by leading VLSI product companies. 

VLSI enthusiasts who want to become self-sufficient with RTL coding and simulation using high quality reference/lab material and free EDA tools**.

Pre-requisites for taking this course:

(a) Bachelor’s degree Electronics Engineering.

(b) Basic knowledge on fundamentals of digital design.

(c) Some familiarity with Verilog RTL coding and UNIX basics will be helpful.

Beyond completion of the lab exercises, following are the mini-projects that the students will work on towards the end of the course: 

(1) Hierarchical implementation of a design that integrates a shift-register with pattern detect and a counter that uses the pattern detect condition as trigger. The design uses multiple clock-domains with synchronization. The students will also implement a simple testbench to test the functionality. Reference code will be provided. 

(2) A PWM IP with programmable period and an AMBA APB interface for programmation. A reference testbench will be provided for sanity checking of the design. However, the students will be required to implement a testbench on their own to test the design.

Learning Objectives 

→ Set expectations on the course objectives and the completion criteria.

→ Lay a solid foundation for getting into detailed RTL learning exercises and related lab work.

→ Develop familiarity with the lab/project execution environment based on LINUX OS.

Topics 

Overview of course objectives and the lecture topics planned to be covered in the course.

Overview of labs and projects that the students will conduct hands-on in the LINUX environment.

Overview of Verilog Primer Labs.

Main RTL quality considerations that a professional RTL designer must keep in mind while coding.

Hands-on LABs: 

LAB1 : LINUX environment: Directory structure, basic commands, VI editor. 

LAB1 : Quick-and-dirty compile and simulation of RTL using open-source Icarus Verilog and Gtkwave. 

LAB1 : Compile RTL and bring-up simulations using ModelSim. 

LAB2.1 : Example Code overview of File/IO/VCD example 

Assignment: Execute LAB2.1  

Learning Objectives 

→ Understand all fundamental aspects about clocking that a VLSI engineer must be aware of.

→ Understand the concepts of File/IO/VCD operations in SystemVerilog and related syntax.

Topics 

Essentials of Clocking: 

→ Overview

→ Duty-cycle

→ Synchronous and asynchronous clocks

→ Setup and Hold time, timing requirements

→ Clock-tree, clock-tree cells

→ Phase and path reconvergence.

Hands-on LABs: 

LAB2.1 : Bring up the lab exercises and complete the analysis of File/IO/VCD  SystemVerilog example.

LAB2.2 : Example code overview of behavioral Vs structural RTL and Blocking Vs Non-Blocking assignments, understand the expected code behavior.

Assignment: Execute LAB2.2

Learning Objectives 

→ Understand the most commonly used clock-gating techniques in depth.

→ Internalize the concept of synchronization, its background, techniques and related timings.

→ Understand the difference between behavioral and structural coding styles.

→ Internalize the concepts of blocking and non-blocking assignments, and their usage.

Topics 

Clock-gating:

→ Need for clock-gating.

→ Simple AND based clock-gating and related timing diagrams.

→ Latch + AND based clock-gating circuit, related timing diagrams and DFTM consideration.

Synchronization:

→ Sources of timing failures across asynchronous clock boundaries and the need for synchronization.

→ Typical 2-stage synchronizer circuit and related timing diagrams.

→ An example of how selective synchronization can be deployed across asynchronous boundaries, explained using timing diagrams.

→ The concept of MTBF and how MTBF can be improved using a 3-stage synchronizer, explained using timing diagrams.

Hands-on LABs:

LAB2.2  : Bring up the lab exercises and complete the analysis of the SystemVerilog examples for behavioral Vs Structural coding and blocking Vs non-blocking assignments

LAB2.3   : Example code overview of signal drive strengths, functions, 'case', 'if'  and conditional assignments, understand the expected code behavior.

Assignment: Execute LAB2.3

Learning Objectives 

→ Understand the behavior and usage of synchronous and asynchronous Resets in detail.

→ Familiarize the concept of Bus Interfaces and most popular examples.

→ Familiarize the most commonly used side-band signals in an IP/SOC design that all VLSI designers must be aware of.

→ Thorough review of the concept of Signal Drive Strengths and supported signal drive levels in SystemVerilog.

→ Learn the syntax and usage of the three main behavioral constructs in SystemVerilog viz. 'case, 'if' and conditional-assignments.

→ Understand the usage of functions in SystemVerilog.

Topics

Resets:

→ Overview of resets and various uses of resets.

→ The key attributes of asynchronous reset.

→ The key attributes of synchronous reset.

→ The circuit, timing diagrams & code-snippets for asynchronous & synchronous resets.

Bus Interfaces:

→ Overview of bus interfaces

→ Common bus protocols

→ Bus masters and slaves

Typical Side-band signals:

→ Interrupts and events

→ Clock and power management signals

→ IO control signals

→ Emulation and DFTM control signals

Hands-on LABs:

LAB2.3 : Bring up the lab exercises and complete the analysis of the Verilog examples for signal drive strengths, functions, case, if  and conditional assignments

LAB2.4 : Example code overview of Verilog operators and forever/repeat/while loops, understand the expected code behavior.

Assignment: Execute LAB2.4

Learning Objectives

→ Study the difference between Moore and Mealy styles of FSM implementation.

→ Familiarize with the objectives, the techniques used and most commonly used components of Power Management in IPs and SOCs.

→ Get in touch with a complete list of all SystemVerilog operators.

→ Understand in depth how 'foreach', 'repeat' and 'while' loops are used and how the simulator schedules the iterations.

Topics 

Finite State Machine (FSM):

→ Overview and different representations.

→ Two types of Finite State Machine implementations: Moore and Mealy.

Power Management Techniques:

→ Main objectives of implementing power management in SOCs

→ Commonly used Power management techniques 

→ Key components used for implementation of Power management:

     - Voltage Level shifters

     - Retention flip-flops

     - Power switches

     - Isolation cells

Hands-on LABs:

LAB2.4 : Bring up the lab exercises and complete the analysis of the examples for all SystemVerlog operators and 'forever'/'repeat'/'while' loops.

LAB2.5 : Example code overview of User Defined Primitives, tasks and SystemVerilog parameters, understand the expected code behavior.

Assignment: Execute LAB2.5

Learning Objectives 

→ Familiarize with the concept of Power-Performance-Area (PPA) trade-offs and most commonly used knobs for achieving the PPA balance. 

→ Learn the syntax and usage of User Defined Primitives (UDP)

→ Get introduced the Perl coding fundamentals and typical use-case scenarios.

Topics

Power-Performance-Area (PPA) trade-offs:

→ Various knobs that VLSI designers use to balance the Power, Performance and Silicon Area of a device to achieve the optimal requirements. These include:

  - Cell sizing

  - Voltage domains  

  - Power domains

  - Logic cloning

→ Understand the impact of changing each knob on the PPA aspects of the device.

Hands-on LABs:

LAB2.5 : Bring up the lab exercises and complete the analysis of the Verilog examples for User Defined Primitives, tasks and Verilog parameters.

LAB2.6 : Example code overview of  usage of compiler directives in Verilog,  understand the expected code behavior.

LAB3 : Review the Perl example that generates Shift Register SystemVerilog code in order to understand the basic usage of Perl and discuss the Perl exercises.

Assignments: Execute LAB2.6 and LAB3  

Learning Objective

→ Familiarize with the background and techniques related to Design For Test and Manufacturing (DFTM).

→ Understand scan-chain operation in detail.

→ Understand the purpose of ATPG Stuck-At, At-Speed, Boundary-Scan and IDDQ tests which are must-support basic DFTM tests for all devices.

→ Familiarize with the usage of compiler directives in SystemVerilog.

→ Fully analyse the Perl quick start exercises to lay a solid foundation for deeper learning and future application of Perl programming.

Topics 

Design For Test and Manufacturability (DFTM):

→ The background of deploying extensive DFTM techniques in modern day designs.

→ Most commonly used DFTM techniques and the major steps involved in accomplishing the DFTM implementation

→ A detailed analysis of the scan-chain operation that forms the basis of most DFTM tests.

→ ATPG Stuck-At, At-Speed, Boundary-Scan and IQQQ tests, related test coverage requirements and DPPM impact.

Hands-on LABs:

LAB 2.6 : Bring up the lab exercises and complete the analysis of the Verilog example of compiler directives in SystemVerilog.

LAB3 : Analyse the simulation results of the Perl generated SystemVerilog code. Review the reference Perl code that meets the requirements of the shift register code-generator exercise.

LAB4 : Review the pattern detect example implementations of Moore and Mealy FSMs. Discuss the requirements of the FSM implementation expected to be done as part of the exercise.

Assignments: Execute LAB4 exercise

Learning Objective 

→ Familiarize with various stages and interdependencies of Industry standard IP and SOC development flows at a high-level.

→ Understand the major steps involved in the generation of gate-netlist from RTL.

→ Thorough understanding of FSM coding styles through execution and analysis of hands-on exercises.

→ Get introduced to logic synthesis and leaf-cell libraries.

→ Understand how RTL gets mapped to gate-level implementation by means of schematic analysis.

Topics

IP and SOC development cycles - High level overview:

→ Various stages of IP Development cycle from Specification to IP packaging.

→ Various stages of SOC development cycle from Specification to Tape-out.

→ A typical SOC block-diagram showing IP blocks and interface buses

Overview of Gate-netlist generation:

→ The three major steps in the gate-netlist generation:

   - Logic synthesis process

   - Scan insertion in the gate-netlist

   - Formal Verification (Equivalence checks)

Hands-on LABs:

LAB4 : Bring up the lab exercises and complete the analysis of the FSM design that is expected to be completed as part of the exercise.

LAB5 : Review the RTL codes for the shift register and the Mealy FSM implementation  that are planned to be taken through the synthesis experiments.

LAB5 : Walk through the logic synthesis flows for the shift register code implementation and schematic review of the resultant gate-netlist.

LAB5 : Understand the concept of leaf-cell library used during synthesis, using the TSMC018 .lib example.

LAB5 : Discuss the synthesis experiment using the Mealy FSM Verilog code that is expected to be completed as part of LAB5 exercises. 

Assignment: Execute LAB5 exercises

Learning Objective 

→ Familiarize with some of the must-know terminology and major stages of Physical Design implementation.

→ Refresh the knowledge of silicon manufacturing cycle at a high-level.

→ Gain better understanding on how RTL gets mapped to gates through completing the synthesis exercises.

→ Understand the requirements of the first mini-project in detail in order to prepare for implementation and touch-testing.

Topics 

Physical Design flows:

→ A quick snap-shot of various steps involved in converting a gate-netlist to the final tape-out database that goes to the manufacturing units.

→ A typical SOC floorplan created during the physical design process.

Semiconductor device Manufacturing and Packaging:

→ A quick snap-shot of various stages of semiconductor manufacturing after the tape-out of the design, resulting in a packaged silicon device.

Hands-on LABs:

LAB5 : Analyse the results of the synthesis experiment using the Mealy FSM Verilog code, which is expected to be completed as part of LAB5 exercises. 

LAB6 (Mini-Project) :  Review the functionality requirements and reference templates required to implement the shift-pattern detect based counter design. Discuss the usage of a simple testbench in doing a sanity check of the design implementation.

Assignment: Start execution of the LAB6 mini-project

Learning Objective 

→ Understand in depth the two most commonly used bus interface for IP MMR programmation - The AMBA AXI4-Lite and APB.

→ Build confidence through analysis of the reference design implementation for the first mini-project.

→ Understand the requirements of the second mini-project in detail in order to prepare for implementation and touch-testing.

Topics 

AMBA APB and AXI4-Lite Interfaces:

Introduction to AMBA APB and AXI4-Lite Bus interface signals

Typical write and read transaction timing diagrams.

Hands-on LABs: 

LAB6 (Mini-Project1) : Analyse the reference implementation of the shift pattern detect based counter implementation and analyse the expected behavior of the design using simple testbench. 

LAB7 (Mini-Project2) : Review the implementation requirements of a PWM IP with APB MMR interface and programmable period, which is expected to be completed as part of the LAB7 mini-project .Walk through the reference templates and sample testbench that can be used for completion of the LAB7. 

Assignments: Take Mini-Project1 to completion, Execute LAB7 mini-project

Learning Objective 

→ Share information on some useful WEB resources

→ Final review of the two Mini-Projects

Topics 

→ List of useful WEB resources for further learning and reference.

Hands-on LABs:

LAB6/LAB7 Mini-Projects :  Complete analysis of the final implementations of the designs and the simple testbenches that test the basic functionality of the two designs. Suggestions for further enhancements to the designs that can be executed off-line.